1. Field
Microelectronics fabrication, including a method of forming a shallow junction.
2. Description of the Related Art
Advances in semiconductor devices such as Complimentary Metal Oxide Semiconductor (CMOS) devices rely on the miniaturization of the devices. Smaller devices typically equate to faster switching times, which lead to speedier and better performance. Miniaturization of the devices involves scaling down various vertical and horizontal dimensions in the device structure. For example, the thickness of the ion implanted source/drain junction of a p-type or an n-type transistor is scaled down with a corresponding scaled increase in the substrate channel doping.
For devices with a critical gate dimension in the submicron level, e.g., lesser than or equal to 0.1 μm, a shallow junction is required. Additionally, a source/drain extension junction with an abrupt profile slope is required.
The formation of source/drain extension junctions is commonly carried out by ion implantation using the appropriate dopants (e.g., boron and indium for p-type or arsenic and phosphorous for n-type). The device substrate, typically crystalline silicon, is preamorphized with ions such as silicon (Si) or germanium (Ge). Preamorphization is a process by which sufficient amounts of ions are implanted into the substrate to convert the surface region of the substrate from crystalline to amorphous. The depth of the converted region depends on the nature of the ions, ion energy, and the dose of the ions on the substrate.
FIG. 1A illustrates that a silicon substrate is preamorphized to contain an amorphous portion 102. The implantation can be controlled so that only a certain depth D1 (from the top surface) of the silicon substrate is amorphized. The remaining depth of the silicon substrate remains crystalline as illustrated by crystalline portion 104. Typically, the depth D1 is the desired depth for the source/drain junction of the device. A dopant source 106 such as phosphorous, arsenic, boron, or indium is implanted into a region in the amorphous portion 102.
FIG. 1B illustrates that the silicon substrate is annealed using a laser annealing process to diffuse and activate the dopant. Using the laser annealing process enables the creation of a more abrupt junction than would other types of annealing. The laser annealing process also recrystallizes (or regrows) the amorphous portion 102 into a crystalline structure. As shown in FIG. 1B, the dopant 106 fully diffuses over the amorphous portion 102 that has now recrystallized. Typically, the laser annealing process occurs at about 1200° C. to about 1400° C., or at a temperature high enough to melt amorphous silicon.
As can be seen from FIGS. 1A-1B, although the current process may result in an abrupt box-like junction it also creates defects 108 at the amorphous-crystalline interface 110, which is located in close proximity to the junction. The defects 108 are sometimes referred to as End-Of Range (EOR) dislocations. The defects 108 can create several problems for a device.
As illustrated in FIG. 1C, a device 101 is created using the process described above. The device 101 contains shallow source/drain extensions 103 created in a substrate 100 using the process described above. The device 101 also includes source/drain regions 111, a gate 105, which includes a gate oxide 107 overlying the substrate 100 and a polysilicon layer 109 overlying the gate oxide 107, all of which are created using methods well known in the art. Upon annealing, the source/drain extensions 103 are formed with defects 113 at the original amorphous-crystalline interface. The defects 113 enhance dopant diffusion resulting in a deeper source/drain extension junction and poor junction profile. The defects 113 also lead to added leakage and noise in the device. For example, the defects 113 cause leakage across the source/drain extension junction and degrade device performance.